For decades, the computing industry has followed a simple formula: make transistors smaller and put more of them on a chip. This strategy has facilitated the tremendous increase in computing power predicted by Moore’s Law. But as components approach the atomic scale, engineers are increasingly faced with silicon’s physical limitations and the effects of quantum mechanics.
Many researchers believe that the next big breakthrough will not come from shrinking devices further, but from building them upwards.
A team led by Qing Cao, a professor in the University of Illinois Granger College of Materials Science and Engineering, has demonstrated a new method for directly stacking multiple layers of silicon electronics. This approach has the potential to dramatically increase computing density, improve performance, and reduce energy consumption, extending the advances that have propelled the semiconductor industry for more than half a century.
“Consider something as simple as static random access memory, which is common in CPUs and GPUs.Currently, to store one bit of information, you need six blocks called transistors on a single plane. “With vertical integration, you can distribute them across multiple layers. It’s like replacing a vast suburb with a skyscraper. You get the same functionality, but with a smaller space footprint while making communication between layers faster and more efficient.”
The researchers report that the process achieved device yields of 98 to 100 percent while using standard single-crystal silicon, the semiconductor material that underpins modern electronics. The results suggest that the technology could eventually be adopted by commercial chipmakers.
“Vertical integration is already starting to make its way into commercial devices, especially dedicated AI hardware, but monolithic integration is what unlocks the full potential of 3D chips,” said Cao. “For the first time, we met the thermal budget for monolithic 3D integration using standard single-crystalline silicon and achieved unprecedented performance.”
The survey results are naturea journal that rarely publishes research articles on silicon microelectronics.
Why is the semiconductor industry on the rise?
For nearly 60 years, Moore’s Law has guided chip development. This principle predicts that transistor density on integrated circuits will double approximately every two years, leading to faster and more efficient processors.
This trend has held up very well, but it is becoming increasingly difficult to maintain.
“In a sense, we are reaching the limits imposed by physics,” Cao said. “If you look at the actual size of transistors, they’re not getting smaller, especially in terms of the pitch of the contacted gates, because they’re starting to be limited by the inherent material properties of silicon and the fundamental laws of quantum mechanics. If we’re going to continue the trend of increasing microprocessor processing power, we have to start thinking beyond just squeezing more devices onto a single surface.”
Stacking devices vertically is an attractive option. Instead of continuing to shrink individual transistors, engineers can place multiple layers of circuits on top of each other. This not only provides more space for components, but also reduces wiring distances, reduces parasitic capacitance, and significantly increases communication bandwidth between different parts of the chip.
These benefits are especially important for artificial intelligence and other data-intensive computing applications.
The promise of monolithic 3D chips
Current commercially available 3D chip technology already uses stacking, which typically requires semiconductor devices to be fabricated on separate wafers before being bonded together. Examples include high-bandwidth memory and AMD’s 3D V-Cache technology.
Although these methods have been successful, they also have limitations. The alignment between layers is relatively rough, and the vertical connections known as through-silicon vias (TSVs) are relatively large and sparse.
Monolithic 3D integration takes a different approach. Rather than bonding completed wafers together, each new device layer is fabricated directly on top of the previous layer. This allows for higher density vertical connections, shorter distances between layers, and nanometer alignment accuracy.
Researchers have pursued this concept for years because it can increase connectivity between layers by a factor of 10 to 100 compared to traditional stacking methods.
Solving heat problems
The biggest barrier to monolithic integration was temperature.
The production of high-quality crystalline silicon and the manufacture of high-performance semiconductor devices typically require temperatures approaching 1,000 degrees Celsius. However, if metal interconnects are already present in the completed circuit layer, such temperatures will destroy them.
“It is generally accepted in the industry that once the first layer of the circuit is completed, the thermal budget limit for additional layers is 400 degrees Celsius,” Cao said. “Researchers in academia and industry have attempted to get around this problem by using semiconductor materials other than single-crystal silicon for the top layer. However, any resulting devices will inevitably suffer from performance and reliability issues.”
Previous efforts have explored alternative materials such as polycrystalline silicon, amorphous and nanocrystalline metal oxides, carbon nanotubes, and two-dimensional semiconductors. However, these materials often exhibit performance limitations, defects, and mismatch with the underlying silicon transistors.
Low-temperature manufacturing possible with ultra-thin silicon nanomembrane
The Illinois team has developed a process that maintains the benefits of single-crystal silicon while staying well below its thermal limits.
The method begins by creating ultrathin, free-standing silicon nanomembranes from a donor wafer. These membranes are transferred onto a receiving substrate containing already completed circuits using a roll laminator. The bonding process requires temperatures below 200 degrees Celsius.
Because the silicon layer retains its crystalline quality, the resulting device maintains strong performance and reliability while staying safely within the thermal budget required for monolithic integration.
“In addition to being lower cost and easier to implement, our method has several advantages over the traditional approach of stacking silicon wafers,” Cao said. “The thickness of the membranes we transferred is only 10 nanometers or less, compared to typical wafer thicknesses of 500 to 700 micrometers. Because the films are thin, these membranes are mechanically flexible and conform to the underlying surface. This conformality helps avoid interfacial defects such as voids that are common when trying to force two rigid wafers together through wafer bonding.”
High performance due to 3-layer lamination
The researchers also redesigned the transistor architecture.
Traditional transistor manufacturing relies on a process called doping, which introduces impurities into silicon to control its electrical behavior. This process typically requires temperatures in excess of 600 degrees Celsius.
To avoid such temperatures, the team used junctionless transistors. In these devices, the silicon is uniformly and heavily doped before the stacking process begins. The extremely thin silicon film allows effective control by the gate of the transistor, while the high doping level helps reduce parasitic contact resistance.
Using this strategy, the researchers fabricated three stacked layers containing 625 transistors each. This device showed high uniformity and high manufacturing yield.
Their output current density matched that of conventional silicon transistors fabricated on bulk wafers at much higher temperatures. It also performed at least three to four times better than monolithic devices made with alternative materials.
The researchers used vertical metal interconnects to connect the layers and successfully demonstrated three-dimensional logic circuits and static random access memory cells.
For commercial semiconductor manufacturing
According to Cao, the most important result may be the scalability of the process.
“But most importantly, we showed that this process is scalable,” Cao said. “We can continue to stack layers beyond the three layers we demonstrated, and the process yields high-performance transistors with high yield and low variation. We now have a strong foundation to transfer this technology and demonstrate its immediate potential in industrial semiconductor foundries.”
This research was conducted through Illinois Grainger Engineering’s Accelerated Advanced Semiconductor Chip Center. Industry partners for the center include IBM, Intel, and Taiwan Semiconductor Manufacturing Company.
The researchers are now preparing to transfer the technology to industrial semiconductor foundries, an important step toward commercial production of truly monolithic 3D silicon chips.
Other contributors to this study include Bao Lam, Yung Man Yu, Hyunjun Nam, Hsu-Chih Ni, Shomik Chatterjee, Shaloo Rakheja, and Jian-Min Zhuo.
Funding was provided by the National Science Foundation, industry partners at Illinois Grainger Engineering’s Center for Advanced Semiconductor Chips with Accelerated Performance, and the Silicon Crossroads Microelectronics Commons Hub.
